@[email protected] to [email protected]English • 5 months agoWhich new Protocol or Standard are you most excited about?message-square52fedilinkarrow-up188
arrow-up188message-squareWhich new Protocol or Standard are you most excited about?@[email protected] to [email protected]English • 5 months agomessage-square52fedilink
minus-squarepizzaboilinkfedilinkEnglish23•5 months agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-square@[email protected]linkfedilink20•edit-25 months agoIn principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-square@[email protected]linkfedilink5•5 months agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-square@[email protected]linkfedilinkEnglish5•5 months agoI think a register for each of the primes should be enough.
minus-square@[email protected]linkfedilink9•5 months ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-squarecaseyweedermanlinkfedilink3•5 months agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-square@[email protected]linkfedilink3•5 months agoAren’t they more like a hybrid instruction set and architecture?
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
I think a register for each of the primes should be enough.
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?