I was curious how bad 10% was, so I went digging to see what it should be.
A “good” yield target on a modern process is something like 60-70%, so this is a shocking shockingly bad oof, though it’s also not a complete process, so it’s possible they can salvage this and turn it into something viable but, still, oof.
Talking about the “yield” of a process doesn’t make any sense. Yield is a metric for a specific chip fabricated on a given process. This depends heavily on the size of the chip and mitigation techniques.
Yield is the percentage of chips that are functional. Roughly, you can think of it as the probability of a chip having 0 defects. The bigger the chip, or the higher the defect density, the lower this probability becomes. Chip designers will also include mitigation techniques (e.g. redundancy) to allow chips to work even with some defects.
I was curious how bad 10% was, so I went digging to see what it should be.
A “good” yield target on a modern process is something like 60-70%, so this is a shocking shockingly bad oof, though it’s also not a complete process, so it’s possible they can salvage this and turn it into something viable but, still, oof.
Talking about the “yield” of a process doesn’t make any sense. Yield is a metric for a specific chip fabricated on a given process. This depends heavily on the size of the chip and mitigation techniques.
The “correct” metric to compare processes is defect density (in defects per square cm). Intel claims that their defect density is below 0.4 defects/cm²: https://www.tomshardware.com/tech-industry/intel-says-defect-density-at-18a-is-healthy-potential-clients-are-lining-up. This would be relatively high but not much worse than what TSMC has seen for their recent nodes: https://www.techpowerup.com/forums/threads/intel-18a-process-node-clocks-an-abysmal-10-yield-report.329513/page-2#post-5387835).
Does this mean that errors happen on a later stage of production? How do we get from defects/cm to yield?
Yield is the percentage of chips that are functional. Roughly, you can think of it as the probability of a chip having 0 defects. The bigger the chip, or the higher the defect density, the lower this probability becomes. Chip designers will also include mitigation techniques (e.g. redundancy) to allow chips to work even with some defects.